Field of the Invention
The invention relates to a latch-up test device and a latch-up test method, and more particularly, to a latch-up test device and a latch-up test method capable of testing a wafer under test.
Description of Related Art
A latch-up effect is an important factor that influences a reliability of an integrated circuit, and thus a test for an anti-latch-up capability is usually performed on the integrated circuit before leaving the factory. Generally, a manufacturing process of the integrated circuit includes a circuit design, a chip fabrication and a chip packaging. Further, in conventional latch-up test methods, a trigger pulse that increases linearly is utilized to perform a latch-up test on the integrated circuit at the chip packaging stage. However, because said trigger pulse is gradually increased in a linear manner, it often consumes an extremely-long testing time to complete the test for the anti-latch-up capability of the integrated circuit in the conventional latch-up test methods. In addition, since only the integrated circuit at the chip packaging stage can be tested by the conventional latch-up test methods, manufacturers must wait until the integrated circuit is in the last stage of the manufacturing process before determining whether to re-manufacture the integrated circuit, resulting in increases in both the production cost and the production time for the integrated circuit.